1. Field of the Invention
The present invention generally relates to pulse shaping circuits and, more particularly, to clock pulse stretcher/chopper circuits which output pulses of a predetermined pulse width in a manner largely independent of input pulse width.
2. Description of the Prior Art
The information contained in the binary state of any signal in a digital circuit is often a function of the particular time at which a particular binary state exists or changes. Therefore, in the field of digital circuit design, the inherent and unavoidable propagation delay of a signal through any element of a digital circuit, including simple metal connections thereof, must often be considered. For this reason, most digital circuits include arrangements for synchronizing operations for the purpose of establishing a time at which signals are to be sampled or operations performed in regard to signals then existing at inputs to certain circuit elements. It is therefore common to provide one or more clocks, possibly of differing phases, for control of the timing of operation of most digital circuits. Such a clock is also useful in the reshaping of digital signals both as to amplitude and duration as such digital signals are propagated through a digital circuit.
It is, of course, a complicating factor in the design of digital circuits that clock signals are also subject to propagation delays and other forms of distortion as they are distributed to various elements of a digital circuit and circuits for reshaping clock signals are well-known. In particular, the duration of a pulse of a clock signal may be critical to the operation of a particular digital circuit or one or more portions thereof. Accordingly, a type of circuit known as a pulse stretcher/chopper has been developed to produce a pulse of predetermined duration in response to a particular event such as the change of state of a particular signal in the system, such as a clock signal.
One known type of circuit used for this purpose is the so-called relaxation oscillator or monostable flip-flop which uses a circuit with a time constant, such as an RC circuit, to determine the output pulse duration. The same effect can be achieved with a logic circuit such as an EXCLUSIVE-OR or AND gate by using a similar time constant circuit to introduce a delay or phase shift between inputs thereto of a common signal.
Further, the recovery period (e.g. the period between completion of an operation in response to an input event and the time the circuit becomes able to respond to another input event) for such circuits after the termination of an output pulse is often excessively long for use with high-speed digital circuits or where extreme duty cycles of input or output signals are involved. Since the recovery period of the circuit must ordinarily be matched by the duration of an inactive state of the input signal and/or the pulse shaping circuit, itself, the required recovery period not only limits the frequency at which the clock stretcher/chopper can operate but also establishes limits on operating margins which must be provided with respect to the duty-cycle of both the input and output of the pulse stretcher/chopper.
The problem of recovery time has generally not been solved without resort to circuits of substantial complexity. Without complex fast recovery circuitry, the recovery time often approximates one half of the clock cycle time. If the duration of the inactive (e.g. binary 0) period of the input clock pulse is shorter than the delay provided to establish output pulse duration of the pulse stretcher/chopper circuit, glitching or the production of pulses of incorrect duration is very likely to occur. As computing circuitry has been designed to operate at higher clock rates and reduced cycle times, accommodating duty-cycle restrictions on the system clock consistent with noise immunity and dedicating sufficient chip space to complex, high-performance clock stretcher/choppers have both become prohibitive.
Another problem associated with pulse shaping circuits is the fact that the output signal is less than fully controlled by the input signal. This is inherent due to the function of reshaping of the pulse, particularly as to duration. In other words, once an "event" appears to have been detected, if any discrimination is provided at all, the output of the pulse shaping circuit will be determined by the parameters of the pulse shaping circuit rather than the input signal. Since an "event" is usually detected as the leading edge of a pulse, such circuits are often susceptible to being triggered by noise signals or small voltage spikes occurring in the system. Since digital circuits usually operate to develop rapid transitions in voltage between binary logic states, a tendency to develop such noise signals is also inherently present. Therefore, unless relatively sophisticated noise rejection or pulse width discrimination circuitry is employed, spurious operation of the pulse shaping circuit may occur.
An example of a pulse shaping circuit including pulse width discrimination circuitry is disclosed in U.S. Pat. No. 4,636,735 to R. A. Wargo in which signals of less than a predetermined duration are propagated without increasing the pulse length, but with a substantial delay. Pulses of greater than a predetermined duration are stretched by a predetermined amount. However, this circuit is not capable of producing an output pulse of a specific, predetermined duration. That is, if the input pulse is longer than a predetermined duration, the output pulse will be of the duration of the input signal but increased by a predetermined duration.
Due to the complexity of digital circuits at the present time, it is becoming more desirable to provide pulse reshaping circuits such as clock stretcher/choppers on each chip which includes clocked logic or must perform accurately timed operations. An example of such an implementation is shown in U.S. Pat. No. 4,754,164, to L. P. Flora et al. which utilizes a relatively large strip delay line on the chip to achieve de-skewing of a clock signal. For this reason, the complexity of such circuits or size of the components thereof, as in the Flora et al. patent, which has been required to achieve adequate noise immunity and fast recovery time has recently become more objectionable since the footprint of such a circuit commonly limits the portion of the surface of the chip on which the remainder of the chip circuitry can be formed.